The present invention relates to circuit extraction in integral circuit (IC) design processes. More particularly, the present invention relates to a method and apparatus for calculating resistance of a conductor layer for an IC design.
As complexity and performance of IC and Very Large Scale Integration (VLSI) circuit increases, time delay due to interconnects is becoming as significant as that of logic gates. Interconnect resistance (or wire resistance) is one of the important parameters for such a time delay calculation and other circuit characterization.
Interconnects are typically formed with a thin-film, i.e., a two-dimensional metal or conductor layer. Thus, interconnect resistance is typically calculated using the sheet resistance Rs, which is measured in Ohms per square (xcexa9/xe2x96xa1). The sheet resistance Rs takes the material properties and thickness into account, and the resistance of a square unit of material is the same for a square of any size. Thus, the resistance of a conductor layer is calculated as the product of the sheet resistance Rs and the number of squares S. However, there are no formulas for the number of squares S except for conductor layers having the simplest geometry such as a rectangle.
FIG. 1A illustrates a simple rectangular conductor having a length L and a width w. The current flows through the length L from one end to the other, perpendicular to the width w. In this case, the number of squares S is given as S=L/w. However, conductor shapes can be more complicated, for example, as shown in FIG. 1B. Suppose that the current enter the conductor from one edge 11 to another edge 13, current paths need not be straight. This makes it difficult to define a length and a width of the conductor shape, and renders the resistance calculation inaccurate.
Various electronic design automation (EDA) software tools are used for calculating resistance of interconnects or conductor layers. Some software tools (such as those referred to as field solvers) calculate resistance of interconnects by dividing an design area including the interconnects into a small mesh, and calculating potential at each grid points. However, such a potential field calculation takes a substantial amount of time.
A variational method is used for calculating resistance of a conductor layer for an integrated circuit design, the conductor layer having a geometric shape defined by boundary edges. The method includes (a) partitioning the geometric shape into a plurality of rectangular regions, (b) determining at least one source edge and at least one sink edge from among the boundary edges, a current entering the conductor layer through the source edge(s) and leaving the conductor layer through the sink edge(s), (c) setting boundary conditions with respect to the current for each of the rectangular regions, (d) calculating power for each of the rectangular regions with the boundary conditions, (e) calculating power for the conductor layer based on the power and the boundary conditions of each of the rectangular regions, and (f) obtaining the resistance of the conductor layer by minimizing the power dissipation of the conductor layer.